In IC manufacturing where there is a high density of components (e.g., transistors) formed in a substrate (such as a silicon wafer), it is sometimes desirable to interconnect the components using a multi-tier grid of traces. After the components are formed in the substrate, a first thin dielectric layer is formed and patterned to expose contact areas of the components. The openings in the dielectric are then filled with a conductive material, such as aluminum, to form a first tier conductor layer. Horizontal metal traces with vertical “via plugs” may be formed to interconnect the components. Due to the high density of components, providing routing between components without the conductors intersecting may be impractical. Therefore, a second dielectric layer is formed over the first tier conductor layer and patterned to form vias (holes) extending to either the silicon or to conductors in the first tier conductor layer. The vias are then filled with a conductive material (e.g., aluminum) to form vertical interconnections, and another set of horizontal metal traces are formed. There may be more layers of both horizontal and vertical conductors, depending on the complexity of the required interconnects.
In another application for vias, components are formed in a first silicon wafer. Through-Silicon-Vias (TSV's) are etched through the silicon, and the vias are filled with a conductive material to form conductive paths extending between opposing surfaces of the silicon wafer. The vias, if sufficiently large, are typically filled using PVD, CVD, sputtering, plating, or printing a conductive paste. In some cases, the vias only extend part way through the silicon, and the silicon is then thinned (e.g., by CMP) to cause the vias to extend through the wafer. Another wafer or multiple wafers have their electrodes aligned with the conductive vias and the wafers are then bonded together, where the vias create a vertical conductive path through one or more wafers to interconnect components on different wafers to form a 3-D module. The bonded wafers are then diced and packaged. Such TSV's allow wafers formed using very different technologies to be interconnected near the end of the manufacturing flow to create compact 3-D modules after singulation.
A passive interposer wafer may also be fabricated with a pattern of metal-filled vias that extend from the top surface to the bottom surface. The interposer is then sandwiched between two other wafers to electrically connect components on the two wafers.
As the density of components increases, the diameters of the vias must decrease, such as to a few microns. One conventional metal deposition technique is sputtering. Due to the shadow effect, for narrow vias, only the sputtered metal particles that have a trajectory approximately normal to a via opening fill the via. The acceptable angles are reduced as the depths of the vias are increased. The angle of impact of the metal particles is essential random. Hence, there is a relatively high likelihood of open circuits and low yields. Sputtering is a relatively expensive process, with considerable waste of material and the requirement for a vacuum chamber. Other deposition processes, such as plating a seed layer, suffer from the same or additional drawbacks. One common drawback is that the top portion of a via gets clogged with the deposited metal, preventing additional metal from filling the bottom of the vias.
Additionally, there is strain introduced by the mismatch in thermal coefficients of expansion (TCE) of the metal and the silicon, which may lead to cracking.
The same issues regarding vias apply to non-silicon applications.
What is needed is an improved technique for filling vias that is less expensive and more reliable. Additionally, it is desirable to reduce the minimum size of a via to increase the silicon surface area used for forming components.